Makefile

Rules:
$@
The full target filename. By target, I mean the file that needs to be built, such as a .o file being compiled from a .c file or a program made by linking .o files.
$*
The target file with the suffix cut off. So if the target is prog.o, $* is prog, and $*.c would become prog.c.
$<
The name of the file that caused this target to get triggered and made. If we are making prog.o, it is probably because prog.c has recently been modified, so $< is prog.c.

The full list of default rules and variables:

make -p > default_rules
# POSIX-standard make has a specific recipe for compiling a .o object file from a .c source code file:
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $*.c

Make template:

P=program_name
OBJECTS=
CFLAGS = -g -Wall -O3
LDLIBS=
CC=c99
$(P): $(OBJECTS)

Passing enviroment variable:

html:
    latex -interaction batchmode $(f)
    latex2html $(f).tex

...and execute:

f=tip make